The present invention relates generally to a voltage monitoring circuit, and in particular, to a voltage monitoring circuit in a semiconductor device.
Generally, in an integrated circuit, a supply voltage to the individual parts of the circuit reaches a proper voltage level only after a transient period. During such a transient period, a low supply voltage at a value less than the proper voltage level is typically blocked from being supplied to the internal circuit to prevent any malfunction of the internal circuit.
A conventional voltage monitoring circuit, as shown in FIG. 1, generally includes a external supply voltage receiver 10 which is charged by an external supply voltage to produce a charged voltage. This voltage is input to a watched voltage detecting section 20, which inverts its output if the charged voltage of the external supply voltage receiver 10 reaches a predetermined level. An inverter 30 inverts the output signal of the watched voltage detecting section 20.
In the conventional circuit of FIG. 1, when the external supply voltage is switched on, a P-type metal oxide semiconductor (PMOS) transistor 12 in the external supply voltage receiver 10 is turned on, and thus a capacitor 14, connected to a first node N1, begins to be charged. As the capacitor 14 is charged, a voltage level going high at the first node N1. When this N1 voltage reaches a trip point, a PMOS transistor 22 and an N-type metal oxide semiconductor (NMOS) transistor 24 in the voltage detecting section 20 are tripped. Then, the voltage level of a second node N2 shifts from an initial high to a low level, which causes the output .phi.VCCH to shift from an initial low to a high level.
The timing of the output inversion is determined by the resistance value of the PMOS transistor 12 acting as a diode, the capacitance value of the capacitor 14, and the adjustment of the trip points of the voltage detection section 20 and the inverter 30.
However, the conventional voltage monitoring circuit as described above may malfunction due to the output .phi.VCCH of the inverter 30 being shifted at a lower voltage level than desired. The lower voltage level can be caused by a transient delay between supply voltage and the voltage actually realized at the first node N1.
Also, the shift point of the output of the inverter 30, which is the detected voltage level, is restricted to a threshold voltage level Vt of the NMOS transistor 24 of the detecting section 30. Therefore, it is impossible to trigger the shift of the output in this circuit at a higher voltage level than the threshold voltage.
FIG. 2 is a schematic circuit diagram of another conventional voltage monitoring circuit which is constructed to heighten the detected level of the monitored voltage in comparison to the voltage monitoring circuit of FIG. 1. Referring to FIG. 2, the circuit further comprises a watched voltage adjusting section 50 coupled between the source of an NMOS transistor 44 of the voltage detecting section 40 and ground.
The watched voltage adjusting section 50 comprises an NMOS transistor 52 whose gate and drain are connected to each other so as to act as a diode. The watched voltage adjusting section 50 operates to raise the trip point of the inverter as high as the threshold voltage Vt of the NMOS transistor 52.
FIG. 3 is a schematic circuit diagram of still another conventional voltage monitoring circuit which comprises a voltage detecting section 60 including n stages of inverters, and a detected voltage adjusting section 70 with n-1 adjusting stages coupled between the respective inverter stages and ground. In the multi-stage detected voltage adjusting section 70, as the ordinal number of the inverter stages increases, the number of diodes connected to each successive inverter decreases proceeding toward the final inverter stage 52, which lacks any adjusting stage or diode altogether.
One disadvantage of the voltage monitoring circuit of FIG. 3 is that as the power is 20 repeatedly switched on and off, the second and third nodes N2 and N3 in the inverter stages 62, 64 and 66, 68 tend to discharge to the threshold voltage level Vt of "1" V rather than to a "0" V. This effect causes the other inverters to weakly switch on, creating a DC current path between the supply voltage and ground. Thus, the FIG. 3 circuit suffers unnecessary power consumption.
Further, in order to raise the shifting point of the second node N2 as much as n times the threshold voltage Vt, n-1 added stages of inverters are required, which results in circuit complexity and the increase of the layout area. Also, the shifting point of the inverter's output is easily affected by a temperature change due to the sensitive nature of the diodes.
Accordingly, a need remains for a voltage monitoring circuit for adjusting the actual voltage level to a proper level while maintaining stable circuit characteristics against the varying environment, such as temperature change and process parameters and low power consumption parameters.